Linux – Networking This forum is for any issue related to networks or networking. Ask a related question Ask a new question. Reluctant to pursue it as we are not using Petalinux:. Please upgrade to a Xilinx. TI is a global semiconductor design and manufacturing company. Once you get your network going you can uncomment the line and you should be good to go after rebooting or else use sudo ifup eth0.
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FYI, Tool and Software tags: Find More Posts by mhbell. Originally Posted by Chinaman Is this the same as your mobo?
If you have further questions related to this thread, you may click “Ask a related question” below. Is this the same as your mobo?
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Marvell 88E1111 Reset Sequence
Firstly the Ubuntu devs removed the sk98lin stuff because the skge driver was the replacement. I then grabbed all the debs I needed using the network liinux performing a standard upgrade to hoary. Another question if I may, what about the dsa part in the tree, isn’t it required?
I used forcedeth for the driver and all worked fine for most Distros. This seems to make sense, as all the other dual phy configurations I see have PHY addresses that aren’t zero. I have verified that I can read the OUI bits from the PHY registers using u-boot mdio read 0 2, mdio read 1 2 – other addresses do not respond.
Marvell Gbit LAN PHY 88E Compatibility
According to a Xilinx FAE: My network is Mbit. Mentions Tags More Cancel. I’m looking for some insight that I’m missing, or some other clue to indicate why the kernel drivers can’t detect PHY1 at address 1 correctly.
The problem is that it used to use the sk98lin driver provided by the vendor syskonnect but the kernel guys decided to replace it with skge in January On my board, the ping fails. What I did was install warty first because the sk98lin driver there works. The U-boot used is a and the Linux used is the Ti 2.
Linux source code: drivers/net/phy/marvell.c (v) – Bootlin
net/phy: Fix copper/fiber auto-selection for 88e1111 [Linux 2.6.27]
July 13th, 6. We have tried to apply the patch, but does’nt works If you’d like to contribute content, let us know.
Note that I am using two different sub-nets – the I assume you use the same interface voltage for both PHY chips.